oh nice, thanks! totally an oversight when I was in there. how visible is this under /sys/devices/system/cpu/cpu*/cache/index*/shared_cpu_list before the fix? I'm not sure how much Linux fixes this up, or if it faithfully communicates the wrong topology to userland. if this is legible to a booted guest, we probably should have been looking for this in guest_cpu_topo_test.

so, if this is legible in the guest, could you adjust that test to check index*/shared_cpu_list is reasonable too? that is, index0 and index1 are shared across two cores (if SMT is enabled! which, oh dear, the test doesn't assert..), that index2 is shared across all cores, and that there aren't more cache levels?

(.. I also see that in retrospect that test assumes SMT siblings are adjacent in APIC ID, which is definitely wrong in general.)

This is what I get before the patch

root@archiso ~ # cat /sys/devices/system/cpu/cpu*/cache/index*/shared_cpu_list
0
0
0
0-3
1
1
1
0-3
2
2
2
0-3
3
3
3
0-3

which indeed shows each vCPU as its own private L1 and L2 cache.

After the patch I get

root@archiso ~ # cat /sys/devices/system/cpu/cpu*/cache/index*/shared_cpu_list
0-1
0-1
0-1
0-3
0-1
0-1
0-1
0-3
2-3
2-3
2-3
0-3
2-3
2-3
2-3
0-3

Let me add a test for this

Also I just noticed the sibling_idx here

I fixed the sibling_idx calculation in Fix thread_siblings assertion in guest_cpu_topo_test and added the test in Add cache topology verification to guest_cpu_topo_test. It passes for me locally now.

Also noticed this late

that index2 is shared across all cores, and that there aren't more cache levels?

Do you mean index3 😅/L3 which should be shared across all cores? Index 0 and 1 is split among L1i and L1d.

root@archiso ~ # cat /sys/devices/system/cpu/cpu0/cache/index0/level
1
root@archiso ~ # cat /sys/devices/system/cpu/cpu0/cache/index1/level
1
root@archiso ~ # cat /sys/devices/system/cpu/cpu0/cache/index2/level
2
root@archiso ~ # cat /sys/devices/system/cpu/cpu0/cache/index3/level
3

I added test for L1 and L2 to be shared among SMT siblings and L3 to be among all CPUs in Add cache topology verification to guest_cpu_topo_test